FIG. 1(a) is a functional block diagram of a conventional frequency synthesizer. A control-voltage signal Vcntl is delivered from a control-voltage generating device 10, which is composed of a phase detector (PD) or a phase-frequency detector (PFD) 11, a charge pump 12 and a loop filter 13, into a voltage-control oscillator (VCO) 14. In accordance with the voltage level of the control-voltage signal Vcntl, the voltage-control oscillator (VCO) 14 delivers a pair of differential analog signals fp0 and fp180 into a differential-to-single-ended buffer circuit 15. The differential analog signals fp0 and fp180 are converted into a single-ended signal and further amplified into a digital signal Fvco by means of the differential-to-single ended buffer circuit 15. Such digital signal Fvco is fed back into the phase detector (PD) or the phase-frequency detector (PFD) 11 by a divided-by-N counter 17 to be compared with a reference frequency signal Fref and thus control the voltage level of the control-voltage signal Vcntl. Therefore, a digital signal Fvco with a stable waveform is obtained in accordance with the relation of Fvco=Fref×N.
FIGS. 2 and 3 are respectively circuit diagrams of the voltage-control oscillator 14 and the differential-to-single-ended buffer circuit 15. The voltage-control oscillator 14 includes three delay circuits DELAY 1, DELAY 2 and DELAY 3 for processing the control-voltage signal Vcntl and thus outputting the pair of differential analog signals fp0 and fp180. The differential-to-single-ended buffer circuit 15 is implemented by employing four MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), i.e. MN1, MN2, MP1 and MP2, and two inverters, i.e. INV1 and INV2. The operation and principle of the differential-to-single-ended buffer circuit 15 are well known in the art and need not be further described in details herein. Since the loads on the drain terminals MN1 and MN2 are asymmetrical, the duty cycle would possibly be distorted. In addition, the bandwidth of the differential-to-single-ended buffer circuit 15 might vary with the extrinsic parameters, for example device processing temperature, voltage and/or frequency of the frequency synthesizer, the variation of which also distorts the duty cycle. Especially when the frequency synthesizer is operated at different frequencies, the duty cycle distortion is beyond control. For example, the data transfer rate of a CD-ROM/DVD-ROM read-out circuit for the radially outer portion of a disc is approximately 2.5 times as large as that for the radially inner portion. Therefore, the duty cycle distortion occurs due to the frequency difference in the same oscillator. For the above reasons, it is difficult to effectively maintain the duty cycle of the digital signal Fvco at 50%.
The distortion of the duty cycle of the digital signal Fvco away from 50% will result in a poor bit-error rate and an inferior lock-in range of a clock and data recovery circuit, and is thus required to be improved. The prior art with reference to FIG. 1(a) uses a divide-by-two circuit 16 connected with the differential-to-single-ended buffer circuit 15 to solve this problem. By dividing the frequency of the digital signal Fvco by two, the duty cycle distortion can be disregarded, and a pulse signal CLKO of a duty cycle 50% is obtained, as shown in FIG. 1(b).
However, the above frequency synthesizing method has some disadvantages. For example, the frequency of the digital signal Fvco has to double in advance in order to obtain the pulse signal CLKO of a desired frequency. Thus, the power consumption of the frequency synthesizer and the complexity of the divide-by-two circuit 16 are increased. This disadvantage is apparent especially when the working frequency of the current central processing unit (CPU) is as high as several gigahertz.